1. Technical Field
The inventive concept relates to a semiconductor memory device, and more particularly, to a semiconductor memory device with reduced power noise.
2. Discussion of Related Art
A semiconductor memory device such as a flash memory device receives an external power supply voltage having a low voltage level (e.g., 1.8 V) and generates an internal boosted voltage having a voltage level (e.g., 10 V) that is higher than the power supply voltage to perform program, erase and read operations. Accordingly, a nonvolatile semiconductor memory device includes a boosting circuit for receiving a power supply voltage to generate a boosted voltage, a core unit including a memory cell array, and a logic circuit for controlling the boosting circuit and the core unit and inputting/outputting data to/from the exterior. The boosted voltage generated by the boosting circuit is applied to the memory cell array and used to program, erase and read data stored in a plurality of memory cells in the memory cell array.
When the boosting circuit generates the boosted voltage, particularly, when it begins to generate the boosted voltage, current consumption may suddenly increase. The logic circuit, operating with the power supply voltage, controls the semiconductor memory device and can perform various operations to input/output data even while the boosting circuit is generating the boosted voltage. Accordingly, current consumption occurs in the logic circuit, as well as in the boosting circuit, when the boosting circuit is generating the boosted voltage; further contributing to the sudden increase in current consumption. This sudden change in current consumption may generate a surge or power noise that can obstruct the stability of the level of the power supply voltage. For example, the power supply voltage may be leveled down because the power noise has a greater influence on the logic circuit since the logic circuit operates with a power voltage that is lower than a boosted voltage used to operate the memory cell array. The leveled-down power supply voltage may cause the boosted voltage to be leveled down, which can retard data program, erase and read operations for memory cells, thereby resulting in a reduced operation speed of the semiconductor memory device. Further, the leveled-down power supply voltage may cause the logic circuit to malfunction, potentially resulting in a fatal error in the semiconductor memory device.
In addition, the power noise may be generated solely by the boosting circuit when it generates the boosted voltage and also when current consumption in the logic circuit increases due to performing various operations of the semiconductor memory device while the boosting circuit does not operate. The applied power supply voltage itself may include power noise.
Accordingly, there is a need to reduce the effect of power noise on a semiconductor memory device.